Receiver with mirror frequency suppression

ABSTRACT

Receiver comprising an RF front end circuit for a selection and conversion of an RF input signal into a pair of quadrature IF (intermediate frequency) signals being supplied through in-phase and phase quadrature signal paths to signal inputs of quadrature phase detection elements, such as in-phase and phase quadrature phase detectors included in a (PLL) phase locked loop, an output of the quadrature phase detection elements being coupled through a loop filter to a control input of a quadrature IF oscillator supplying a pair of quadrature IF oscillator signals to carrier inputs of the quadrature phase detection elements. To suppress amplitude and phase mismatch deteriorating proper mirror cancellation the quadrature phase detection elements is coupled to amplitude and phase error signal for a detection of amplitude and phase errors in the output signal of the quadrature phase detection elements and a quadrature frequency doubler is coupled between the quadrature local oscillator and carrier inputs of the amplitude and phase error detection means to supply respectively thereto in-phase and phase quadrature error detection carrier signals at twice the IF carrier frequency of the pair of quadrature IF signals, the amplitude and phase error detection means respectively providing amplitude and phase error signals through first and second low-pass filters to an amplitude correction circuit and a phase correction circuit preceding at least one of the inputs of the quadrature phase detection elements for a negative feedback of the amplitude and phase errors.

The invention relates to a receiver comprising an RF front end circuitfor a selection and conversion of an RF input signal into a pair ofquadrature signals being supplied through in-phase and phase quadraturesignal paths to signal inputs of quadrature phase detection meansincluded in a (PLL) phase locked loop, an output of said quadraturephase detection means being coupled through a loop filter to a controlinput of a quadrature IF oscillator supplying a pair of quadrature IFoscillator signals through in-phase and phase quadrature IF carrierpaths to carrier inputs of said quadrature phase detection means. Suchreceiver is on itself known, e.g. from German Patent DE 34 12 191.

Signal processing in receivers of this type generally amounts to thefollowing: the RF front end provides broadband selection and automaticgain controlled amplification of a received RF frequency range andcomprises a tuning stage for a conversion of a wanted RF input signalwithin said received RF frequency range to a predetermined fixed IF(intermediate frequency) using a tuning oscillator generating a tuningoscillator signal at a frequency differing from the carrier frequency ofthe wanted RF input signal by said fixed IF. In the known receiver,phase splitting is obtained by the use of quadrature mixers in thetuning stage, providing the above pair of quadrature IF signals.Alternatively, phase splitting may be obtained by the use of resonanceamplifiers such as known from e.g. U.S. Pat. No. 5,220,686 in the RF orIF signal path. The quadrature IF signals are frequency demodulated inthe PLL to obtain the wanted baseband FM modulation signal, which isavailable at an output of the quadrature phase detection means to befurther processed for reproduction. The loop filter selects from anoutput signal of the quadrature phase detection means a control signalfor the IF oscillator varying with the phase differences between thequadrature IF oscillator signals on the one hand and the incomingquadrature IF signals on the other hand. This control signal providesfor a negative feed back of any such phase differences to the inputs ofthe quadrature phase detection means, resulting in the quadrature IFoscillator signals being phase synchronized with the incoming quadratureIF signals.

However, the frequency distribution of the RF transmission signalsthroughout the received RF frequency range gives rise to frequencydispositions, in which a wanted RF signal finds an unwanted RF signallocated around a mirror frequency, i.e. at an RF carrier frequency whichin the receiver folds back in or close to the baseband modulationfrequency range of the wanted RF signal. Such frequency disposition isdepicted in the diagram of FIG. 1A, in which a wanted RF signal Wcarrying a baseband modulation signal s is located around a carrierfrequency f_(W), and the unwanted signal—hereinafter being referred toas mirror signal M—at a carrier frequency f_(M)=f_(W)+2*f_(IF)+Δf, inwhich f_(IF) is the IF receiver frequency and Δf as depicted beingsmaller than the frequency range of the baseband modulation signal s.

In FIG. 1B the frequency disposition of the wanted and mirror signals Wand M is depicted in the IF range after RF/IF conversion in the tuningstage. The RF/IF conversion not only provides down conversion of thewanted RF signal W to a positive frequency f_(IF), but also folds thecarrier frequency of the unwanted mirror signal M around the tuningoscillator frequency f_(TO) to a negative frequency f_(IF)+Δf, occurringwithin the frequency range of the useful baseband signal s of the wantedIF signal W.

The mirror signal M at said negative frequency f_(IF)+Δf can becancelled with an exact RF/IF phase quadrature signal processing. Inpractice, however, amplitude and/or phase errors due to e.g. parasiticeffects, tolerance spread and other sources of mismatch, cannot becompletely avoided and many efforts have been made to obtain mirror orimage rejection by measures such as precise balancing, accuratematching, narrow tolerances, and/or by the use of polyphase filters,such as known from e.g. the article “CMOS Mixers and Polyphase Filtersfor Large Image Rejection” by F. Behbahani et al., published in IEEEJournal of Solid-State Circuits, Volume 36, No. 6, June 2001, pages873-887. The effect of these known measures, however, is limited andresults in partly suppressed mirror signals, such as illustrated in FIG.1C with mirror signal M. Dependent on its frequency location andamplitude, such partly suppressed mirror signal may become noticeable asa strong deterioration of the wanted signal W.

Now, therefore, it is an object of the invention to provide an effectivemirror or image rejection which adds to the image rejection obtained bythe above known measures, and can be used independent therefrom, and/orwhich allows to loosen the amplitude and phase matching requirements forimage rejection in the known RF/IF quadrature signal processing means.

This object is achieved in a receiver as described in the openingparagraph according to the invention, which is characterized by saidquadrature phase detection means being coupled to amplitude and phaseerror detection means for a detection of amplitude and phase errors inthe output signal of said quadrature phase detection means, a quadraturefrequency doubler being coupled between the quadrature IF oscillator andcarrier inputs of said amplitude and phase error detection means tosupply thereto respectively, in-phase and phase quadrature errordetection carrier signals at twice the frequency of said quadrature IFoscillator signals, said amplitude and phase error detection means beingcoupled respectively through first and second low-pass filters to anamplitude correction circuit and a phase correction circuit for anegative feedback of said amplitude and phase errors to said in-phaseand phase quadrature signal paths.

The invention is based on the recognition that demodulation of a pair ofquadrature IF signals which are mutually not precisely equal inamplitude and/or not precisely phase orthogonal, gives rise to a carriersignal E in baseband at 2*f_(IF) carrying the amplitude and phasemismatch or errors, as depicted in FIG. 1D. The larger the amplitude andphase errors, the stronger said 2*f_(IF) carrier signal E, and, asexplained above, also the stronger the mirror signal M. This means thatreduction of said 2*f_(IF) carrier signal E, hereinafter also beingreferred to as mismatch or error signal carrier, will result in asuppression of said mirror signal M.

By applying the invention, both amplitude and phase mismatch of thequadrature IF signals are being detected from said mismatch carrier E at2*f_(IF) and negatively fed back from the output of said quadraturephase detection means to the in-phase and phase quadrature signal paths.As a result of this negative feed back, the mismatch carrier E isstrongly suppressed in both amplitude and phase and along therewith alsothe unwanted mirror signal M in the reproduced wanted basebandmodulation signal s. The invention restores the amplitude symmetry andorthogonal phase shift between the in-phase and phase quadrature IFsignals, hereinafter in short being referred to as quadrature symmetry,and therewith adds to any eventual mirror suppression obtained by theapplication of the above known measures. Apart from the unwanted mirrorsignal M and the mismatch carrier E at 2*f_(IF) the above demodulationof the pair of quadrature IF signals also causes a mirror signal M′ tooccur at a positive baseband frequency 2*f_(IF)+Δf, which does notdepend on any quadrature symmetry mismatch. In view of its frequencydistance with regard to the useful baseband modulation signal s, thismirror signal M′ can easily be suppressed.

Various forms of implementation of the abovementioned negative feedbackof said amplitude and phase errors to said in-phase and phase quadraturesignal paths are possible. An indirect form of negative feedback ofquadrature symmetry errors is on itself known from U.S. Pat. No.4633315.

An embodiment of a receiver according to the invention in which thequadrature symmetry of the RF or IF signals is restored directly ischaracterized by said amplitude and phase correction circuits beingincluded in at least one of the in-phase and phase quadrature signalpaths preceding the quadrature phase detection means.

An embodiment of a receiver according to the invention in which thequadrature symmetry of the IF signals is restored indirectly ischaracterized by said amplitude and phase correction circuits beingincluded in at least one of said in-phase and phase quadrature IFcarrier paths between the quadrature IF oscillator and the quadraturephase detection means.

An embodiment of a receiver according to the invention in which thequadrature symmetry of the RF signals is restored indirectly ischaracterized by the RF front end circuit comprising an RF tuningoscillator supplying a pair of quadrature RF oscillator signals throughin-phase and phase quadrature RF carrier paths to carrier inputs of aquadrature tuning stage, said amplitude and phase correction circuitsbeing included in at least one of said in-phase and phase quadrature RFcarrier paths preceding said quadrature tuning stage.

An embodiment of a receiver according to the invention in which thequadrature symmetry of the RF signals is restored directly ischaracterized by the RF front end circuit comprising a quadrature phasesplitter converting the RF input signal into a pair of quadrature RFsignals followed by said amplitude and phase correction circuitspreceding said quadrature tuning stage.

For a simple implementation, said amplitude correction circuitpreferably comprises a first multiplier included in at least one of saidin-phase and quadrature paths for an amplitude variation of the signalat said input with said amplitude error.

To balance out spurious response and DC offset from the amplitudecorrection circuit, an embodiment of a receiver according to theinvention is characterized by said amplitude correction circuitcomprising a differential stage following said first low pass filterconverting said amplitude error into a differential pair of first andsecond amplitude error signals and supplying the same to said first anda second multiplier, respectively, said first and second multipliersbeing included in said in-phase and phase quadrature paths.

For a simple implementation of the phase correction circuit, anembodiment of a receiver according to the invention is characterized bysaid phase correction device comprising a third multiplier having asignal input coupled to one of said in-phase and quadrature paths and asignal output coupled to a first adder device, which is included in theother of said in-phase and quadrature paths for supplying thereto a partof the signal occurring at said one path to said other path varying withsaid phase error.

To balance out spurious response and DC offset from the phase correctioncircuit, an embodiment of a receiver according to the invention ischaracterized by said phase correction circuit comprising a differentialstage following said second low pass filter converting said phase errorinto a differential pair of first and second phase error signals andsupplying the same to modulation signal inputs of said third and afourth multiplier, respectively, said third and fourth multipliershaving inputs coupled to the phase quadrature and in-phase paths andhaving outputs coupled to said first and a second adder device, whichare included in said in-phase and phase quadrature paths, respectively.

To obtain a proper control signal for quadrature IF oscillator, crossingzero level at phase lock, said quadrature phase detection meanspreferably comprises in-phase and phase quadrature phase detectors,signal inputs thereof being supplied with in-phase and phase quadratureIF signals of said pair of quadrature IF signals, carrier inputs thereofbeing respectively supplied with phase quadrature and in-phase IFoscillator signals of said pair of quadrature IF oscillator signals andin-phase and phase quadrature outputs thereof being coupled to inputs ofa subtracting stage, an output of said subtracting stage being coupledthrough a loop filter to a control input of said quadrature IFoscillator.

An embodiment of a receiver according to the invention using thebaseband FM modulation signal included in the output signal of thequadrature phase detection means is characterized by an output of saidsubtracting stage being coupled to a baseband FM modulation signalprocessor.

An embodiment of a receiver according to the invention allowing toeliminate mirror signals from a wanted baseband amplitude modulationsignal is characterized by quadrature amplitude demodulation means,comprising in-phase and phase quadrature synchronous amplitudedetectors, signal inputs thereof being supplied with said in-phase andphase quadrature IF signals, carrier inputs thereof being respectivelysupplied with said in-phase and phase quadrature IF oscillator signalsand in-phase and phase quadrature outputs thereof being coupled toinputs of an adding stage, an output of said adding stage being coupledthrough a loop filter to a baseband AM modulation signal processor.

These and further aspects and advantages of the invention will bediscussed more in detail hereinafter with reference to the disclosure ofpreferred embodiments, and in particular with reference to the appendedFigures, wherein

FIG. 1A is an amplitude (A)—frequency (f) diagram showing the frequencydisposition of a wanted RF signal carrying a baseband modulation signals, and its unwanted mirror signal within a received RF frequency range;

FIG. 1B is an amplitude (A)—frequency (f) diagram showing the wantedsignal and its unwanted mirror signal within the IF frequency range;

FIG. 1C is an amplitude (A)—frequency (f) diagram showing the wanted IFsignal and its unwanted partly suppressed IF mirror signal;

FIG. 1D is an amplitude (A)—frequency (f) diagram showing the wanted IFsignal, its unwanted partly suppressed IF mirror signal and a mismatchcarrier E at 2*f_(IF) in a baseband frequency range;

FIG. 2A shows a preferred embodiment of a receiver according to theinvention. In the Figures, identical parts are provided with the samereference numbers;

FIG. 2B shows an alternative embodiment of a RF front end circuit foruse in a receiver according to the invention.

FIG. 2A shows a receiver according to the invention comprising an RFfront end circuit 1 being supplied with an RF input frequency range fromantenna means ANT through an RF input RFI and including subsequentlycoupled to said RF input RFI, an RF input stage 2 for a broadbandselection and automatic gain controlled amplification of said RF inputfrequency range, a tuning stage 3 being provided with a quadrature pairof tuning mixers 3′ and 3″ supplied with a pair of quadrature tuningoscillator signals provided by a quadrature tuning oscillator 4 for aconversion of a wanted RF signal within the RF input frequency range toa predetermined fixed IF (intermediate frequency) and simultaneousquadrature phase splitting, resulting in a pair of quadrature IFsignals, the in-phase IF signal thereof being supplied to an in-phasesignal path I, the phase quadrature IF signal thereof being supplied toa phase quadrature signal path Q, and an IF stage 5 for a narrowbandchannel selection and amplification of said pair of quadrature IFsignals. The IF stage 5 may include an IF polyphase filter such as knownfrom the above cited article “CMOS Mixers and Polyphase Filters forLarge Image Rejection” by F. Behbahani et al., published in IEEE Journalof Solid-State Circuits, Volume 36, No. 6, June 2001, pages 873-887. Thefrequency of said pair of quadrature tuning oscillator signals differsfrom the carrier frequency of the wanted RF input signal by said fixedIF. The pair of quadrature IF signals is being supplied from outputs ofsaid IF stage 5 through said in-phase and phase quadrature signal pathsI and Q to signal inputs of quadrature phase detection means 6-8,comprising in-phase and phase quadrature phase detectors 6 and 7respectively, carrier inputs thereof being respectively supplied withphase quadrature and in-phase IF oscillator signals of a pair ofquadrature IF oscillator signals and in-phase and phase quadratureoutputs thereof being coupled to inputs of a subtracting stage 8, anoutput of said subtracting stage 8 being coupled through a loop filter 9to a control input of a quadrature IF oscillator 10. The quadraturephase detection means 6-8 together with the loop filter 9 and thequadrature IF oscillator 10 form a phase locked loop, in which phasedifferences between the pair of quadrature IF signals on the one handand the pair of quadrature IF oscillator signals on the other hand arebeing measured by the quadrature phase detection means 6-8 andnegatively fed back from the output of the subtracting stage 8 throughthe control signal of the quadrature IF oscillator 10 to said pair ofquadrature IF oscillator signals. This results in a suppression of saidphase differences, which is at maximum in the in-lock state of the PLL,in which the pair of quadrature IF oscillator signals is fully phasesynchronized with the incoming pair of quadrature IF signals. In thisin-lock state of the PLL the output signal of the quadrature phasedetection means 6-8 provides the baseband FM modulation signal, which issupplied to a baseband FM modulation signal processor 11 followed by aloudspeaker device 12 for reproduction of said baseband FM modulationsignal.

The receiver described so far corresponds to the above known receiverand needs no further amplification for a proper understanding of theinvention.

As explained above with reference to FIGS. 1A-1D, mismatch in thequadrature RF/IF signal processing, causing the quadrature IF signals tomutually deviate from quadrature symmetry, i.e. to mutually differ inamplitude and/or to mutually differ in phase from a 90° phase shift,deteriorate proper cancellation of mirror signals at negativefrequencies, such as the mirror signal M shown in FIGS. 1A-1D. Accordingto the invention, mirror cancellation is obtained by an accuratedetection and suppression of said amplitude and phase mismatch as willnow be explained in more detail.

Suppose the amplitude mismatch or amplitude error of the pair ofin-phase and phase quadrature IF signals IFI and IFQ in the in-phase andphase quadrature signal paths I and Q, respectively, is δA and the phasemismatch or phase error δΦ is zero. Then with ω_(IF)=2πf_(IF), IFI andIFQ are defined by:

-   -   IFI=(1+δA)* cos ω_(IF)t    -   IFQ=sin ω_(IF)t

With VCOI and VCOQ being the in-phase and phase quadrature IF oscillatorsignals of the pair of quadrature IF oscillator signals, withoutamplitude error δA and with phase error φ with respect to IFI and IFQ,these signals can be written as:

-   -   VCOI=cos(ω_(IF)t+φ)    -   VCOQ=sin(ω_(IF)t+φ)

The quadrature phase detection means 6-8 provides at its output a phasedetector output signal PDOUT, defined by IFI*VCOQ−IFQ*VCOI withamplitude error δA and phase error φ.

-   -   PDOUT=IFI*VCOQ−IFQ*VCOI    -   PDOUT=(1=δA)* cos ω_(IF)t* sin(ω_(IF)t+φ)−sin ω_(IF)t*        cos(ω_(IF)t+φ)    -   PDOUT=cos ω_(IF)t* sin(ω_(IF)t+φ)−sin ω_(IF)t*        cos(ω_(IF)t+φ)+δA* cos ω_(IF)t* sin(ω_(IF)t+φ)    -   PDOUT=sin(φ)+δA* cos ω_(IF)t* sin(ω_(IF)t+φ)

In the in-lock state of the PLL 6-10, the phase error φ is fullysuppressed (φ−22 0) as explained above, resulting in:

-   -   PDOUT=sin(0)+δA/2*2* cos ω_(IF)t* sin(ω_(IF)t)    -   PDOUT=δA/2* sin(2* ω_(IF)t)

This means that in the in-lock state of the PLL 6-10, the amplitude ofthe unwanted mirror signal M is present at the output of the quadraturephase detection means 6-8 as an amplitude modulated signal δA/2*sin(2*ω_(IF)t) at a carrier of two times the intermediate frequencyf_(IF). With a synchronous amplitude detector using an in-phase (i.e.sinus-phase) detection carrier at the frequency 2*f_(IF) and a low passfilter the amplitude error δA can be detected and reduced in a loop withnegative feedback as will be described in further detail hereinafter.

Suppose the pair of in-phase and phase quadrature IF signals IFI and IFQin the in-phase and phase quadrature signal paths I and Q, respectively,having a mutual phase deviation differing from 90° by a phase error δΦwithout amplitude error. Then:

-   -   IFI=cos ω_(IF)t+δΦ* sin(ω_(IF)t)    -   IFQ=sin ω_(IF)t

In the in-lock state of the PLL, i.e. with phase error φ being zero andwithout amplitude error δA and phase error δΦ, the in-phase and phasequadrature IF oscillator signals can be written as:

-   -   VCOI=cos ω_(IF)t    -   VCOQ=sin ω_(IF)t

The quadrature phase detection means 6-8 provides at its output a phasedetector output signal PDOUT, defined by IFI*VCOQ−IFQ*VCOI with phaseerror δΦ only.

-   -   PDOUT=IFI*VCOQ−IFQ*VCOI    -   PDOUT=(cos ω_(IF)t+δΦ* sin ω_(IF)t)* sin ω_(IF)t−sin ω_(IF)t*        cos ω_(IF)t    -   PDOUT=cos ω_(IF)t* sin ω_(IF)t−sin ω_(IF)t* cos ω_(IF)t+δΦ* sin        ω_(IF)t* sin ω_(IF)t    -   PDOUT=0+δΦ* sin ω_(IF)t* sin ω_(IF)t    -   PDOUT=0+δΦ/2* (1−cos (2* ω_(IF)t))    -   PDOUT=δΦ/2−δΦ/2* cos (2* ω_(IF)t)

This means that in the in-lock state of the PLL 6-10, an amplitude errorδΦ is present at the output of the phase detector as an additional phaseerror and at the same time as amplitude modulated signal−δΦ/2 * cos(2*ω_(IF)t) as a carrier of two times the intermediate frequency f_(IF),also being referred to as mismatch or error signal carrier E. With asynchronous amplitude detector using a quadrature phase (i.e.cosinus-phase) detection carrier at the frequency 2*f_(IF) and a lowpass filter the phase error δΦ can be detected and reduced in a loopwith negative feedback as will be described in further detailhereinafter.

According to the invention, the output of said quadrature phasedetection means 6-8 is coupled to amplitude and phase error detectionmeans 13 and 14 being consituted by synchronous amplitude and phasedetectors for a detection of amplitude and phase errors δA and δΦ in theoutput signal of said quadrature phase detection means 6-8 caused byamplitude and/or phase mismatches in the quadrature receiver signalprocessing due to e.g. parasitic effects, tolerance spread and othersources of mismatch. A quadrature frequency doubler 150 is coupledbetween the quadrature IF oscillator 10 and carrier inputs of saidamplitude and phase error detection means 13 and 14 to supplyrespectively thereto in-phase and phase quadrature error detectioncarrier signals at twice said IF carrier frequency, i.e. at 2*f_(IF),said amplitude and phase error detection means 13 and 14 providingamplitude and phase error signals δA and δΦ through first and secondlow-pass filters 15 and 16 to an amplitude correction circuit 17-19 anda phase correction circuit 20-24 preceding the signal inputs of saidquadrature phase detection means 6-8 for a negative feedback of saidamplitude and phase errors δA and δΦ to said in-phase and phasequadrature signal paths I and Q. Due to this negative feed back, anyoccurrence of amplitude and phase errors δA and δΦ in the output signalof the quadrature phase detection means 6-8 is followed by a correctionof these errors in the signals of the in-phase and phase quadraturesignal paths I and Q, resulting in a suppression of the initialamplitude and phase errors and therewith in a suppression of thebaseband mirror signal M, in the given example of FIG. 1D occurring at abaseband frequency Δf.

The frequency doubler 150 may be constituted by a known frequencydoubler such as disclosed in e.g. U.S. Pat. No. 5,389,886.

The amplitude correction circuit 17-19 comprises a differential stage 17following said first low pass filter 15 converting said amplitude errorsignal δA into a differential pair of first and second amplitude errorsignals +0.5δA and −0.5δA and supplying the same to first and secondmultipliers 18 and 19, respectively, said first and second multipliers18 and 19 being included in said in-phase and phase quadrature signalpaths I and Q preceding the signal inputs of quadrature phase detectionmeans 6-8.

The phase correction circuit 20-24 comprises a differential stage 20following said second low pass filter 16 converting said phase errorsignal δΦ into a differential pair of first and second phase errorsignals +0,5δΦ and −0.5δΦ and supplying the same to modulation signalinputs of third and fourth multipliers 21 and 22, respectively, saidthird and a fourth multipliers 21 and 22 having inputs coupled to thein-phase and phase quadrature signal paths I and Q and having outputscoupled through said first and a second adder device 23 and 24 to thephase quadrature and in-phase signal paths Q and I, respectively,preceding the signal inputs of quadrature detection means 6-8.

For the reception of AM signals, the receiver is provided withquadrature amplitude demodulation means 25-27, comprising in-phase andphase quadrature synchronous amplitude detectors 25 and 26, signalinputs thereof being supplied with the above in-phase and phasequadrature IF signals IFI and IFQ, carrier inputs thereof beingrespectively supplied with the in-phase and phase quadrature IFoscillator signals VCOI and VCOQ and in-phase and phase quadratureoutputs thereof being coupled to inputs of an adding stage 27, an outputof said adding stage 27 being coupled through a baseband AM modulationsignal processor 28 to a loudspeaker device 29.

FIG. 2B shows quadrature phase splitting obtained in the RF input stage2 by the use of resonance amplifiers such as known from e.g. U.S. Pat.No. 5,220,686, converting the single phase RF input signal into a pairof quadrature RF signals being supplied to in-phase and phase quadratureRF signal paths. In this alternative embodiment of the RF front endcircuit 1, the amplitude and phase correction means 18, 19 and 21-24,respectively, may be included in said in-phase and phase quadrature RFsignal paths preceding the quadrature tuning stage 3, whereas only asingle phase oscillator signal is needed for an RF to IF conversion ofsaid pair of quadrature RF signals.

The invention is not limited to the embodiments explicitly disclosed. Itmay well be possible without leaving the scope and spirit of theinvention, to dispense with the differential stages 17 and 20 e.g. bycorrecting for both phase and amplitude mismatch in either the in-phasesignal path I only, or in the phase quadrature signal path Q only, or tocarry out such corrective measure indirectly on the signals of thein-phase and phase quadrature IF signal paths I and Q through aquadrature symmetry correction of the in-phase and phase quadrature IFoscillator signals VCOI and VCOQ of the local IF oscillator 10 precedingthe carrier inputs of the quadrature phase detection means 6-8, such ason itself known from U.S. Pat. No. 4,633,315. Such indirect correctionof the quadrature symmetry of the signals in the in-phase and phasequadrature RF signal paths I and Q may well be possible by a correctionof the in-phase and phase quadrature tuner oscillator signals of thetuning oscillator 4 preceding the carrier inputs of the quadrature pairof tuning mixers of the tuning stage 3.

The invention is embodied in each new characteristic and eachcombination of characteristics. Any reference signs do not limit thescope of the claims. The word “comprising” does not exclude the presenceof other elements than those listed in a claim. Use of the word “a” or“an” preceding an element does not exclude the presence of a pluralityof such elements.

1. A receiver comprising: an RF front end circuit, quadrature phasedetectors, a quadrature IF oscillator, an amplitude error detector, aphase error detector, a quadrature frequency doubler, an amplitudecorrection circuit, and a phase correction circuit, wherein the RF frontend circuit is configured for selection and conversion of an RF inputsignal into a pair of quadrature signals that are supplied throughin-phase and phase quadrature signal paths to signal inputs of thequadrature phase detectors, which are included in a (PLL) phase lockedloop, an output of the quadrature phase detectors are coupled through aloop filter to a control input of the quadrature IF oscillator, thequadrature IF oscillator is configured to supply a pair of quadrature IFoscillator signals through in-phase and phase quadrature IF carrierpaths to carrier inputs of the quadrature phase detectors, thequadrature phase detectors are coupled to the amplitude and phase errordetectors for a detection of amplitude and phase errors in the outputsignal of the quadrature phase detectors, the quadrature frequencydoubler is coupled between the quadrature IF oscillator and carrierinputs of the amplitude and phase error detectors to supply theretorespectively, in-phase and phase quadrature error detection carriersignals at twice the frequency of the quadrature IF oscillator signals,and the amplitude and phase error detectors are coupled respectivelythrough first and second low-pass filters to the amplitude correctioncircuit and the phase correction circuit for a negative feedback of theamplitude and phase errors to the in-phase and phase quadrature signalpaths.
 2. A receiver as claimed in claim 1, wherein the amplitude andphase correction circuits are included in at least one of the in-phaseand phase quadrature signal paths preceding the quadrature phasedetectors.
 3. A receiver as claimed in claim 1, wherein the amplitudeand phase correction circuits are included in at least one of thein-phase and phase quadrature IF carrier paths between the quadrature IFoscillator and the quadrature phase detectors.
 4. A receiver as claimedin claim 1, wherein the RF front end circuit comprises an RF tuningoscillator that is configured to supply a pair of quadrature RFoscillator signals through in-phase and phase quadrature RF carrierpaths to carrier inputs of a quadrature tuning stage, and the amplitudeand phase correction circuits are included in at least one of thein-phase and phase quadrature RF carrier paths preceding the quadraturetuning stage.
 5. A receiver as claimed in claim 1, wherein the RF frontend circuit comprises a quadrature phase splitter that is configured toconvert the RF input signal into a pair of quadrature RF signalsfollowed by the amplitude and phase correction circuits preceding thequadrature tuning stage.
 6. A receiver as claimed in claim 1, whereinthe amplitude correction circuit comprises a first multiplier includedin at least one of the in-phase and quadrature paths for an amplitudevariation of the signal at the input with the amplitude error.
 7. Areceiver as claimed in claim 6, wherein the amplitude correction circuitcomprises a differential stage following the first low pass filterconverting the amplitude error into a differential pair of first andsecond amplitude error signals and supplying the same to the first and asecond multiplier, respectively, and the first and second multipliersare included in the in-phase and phase quadrature paths.
 8. A receiveras claimed in claim 7, wherein the phase correction device comprises athird multiplier having a signal input coupled to one of the in-phaseand quadrature paths and a signal output coupled to a first adderdevice, and the first adder device is included in the other of thein-phase and quadrature paths for supplying thereto a part of the signaloccurring at the one path to the other path varying with the phaseerror.
 9. A receiver as claimed in claim 8, wherein the phase correctioncircuit comprises a differential stage following the second low passfilter that is configured to convert the phase error into a differentialpair of first and second phase error signals and to supply the same tomodulation signal inputs of the third and a fourth multiplier,respectively, the third and fourth multipliers having inputs coupled tothe phase quadrature and in-phase paths and having outputs coupled tothe first and a second adder device, which are included in the in-phaseand phase quadrature paths, respectively.
 10. A receiver as claimed inclaim 1, wherein the quadrature phase detectors comprise in-phase andphase quadrature phase detectors, signal inputs thereof being suppliedwith in-phase and phase quadrature IF signals of the pair of quadratureIF signals, carrier inputs thereof being respectively supplied withphase quadrature and in-phase IF oscillator signals of the pair ofquadrature IF oscillator signals and in-phase and phase quadratureoutputs thereof being coupled to inputs of a subtracting stage, anoutput of the subtracting stage being coupled through a loop filter to acontrol input of the quadrature IF oscillator.
 11. A receiver as claimedin claim 10, wherein the output of the subtracting stage is coupled to abaseband FM modulation signal processor.
 12. A receiver as claimed inclaim 1, further including a quadrature amplitude demodulator,comprising in-phase and phase quadrature synchronous amplitudedetectors, signal inputs thereof being supplied with the in-phase andphase quadrature IF signals, carrier inputs thereof being respectivelysupplied with the in-phase and phase quadrature IF oscillator signalsand in-phase and phase quadrature outputs thereof being coupled toinputs of an adding stage, an output of the adding stage being coupledthrough a loop filter to a baseband AM modulation signal processor. 13.A receiver as claimed in claim 3, wherein the amplitude correctioncircuit comprises a first multiplier included in at least one of thein-phase and quadrature paths for an amplitude variation of the signalat the input with the amplitude error.
 14. A receiver as claimed inclaim 4, wherein the amplitude correction circuit comprises a firstmultiplier included in at least one of the in-phase and quadrature pathsfor an amplitude variation of the signal at the input with the amplitudeerror.
 15. A receiver as claimed in claim 5, wherein the amplitudecorrection circuit comprises a first multiplier included in at least oneof the in-phase and quadrature paths for an amplitude variation of thesignal at the input with the amplitude error.
 16. A receiver as claimedin claim 13, wherein the amplitude correction circuit comprises adifferential stage following the first low pass filter converting theamplitude error into a differential pair of first and second amplitudeerror signals and supplying the same to the first and a secondmultiplier, respectively, and the first and second multipliers areincluded in the in-phase and phase quadrature paths.
 17. A receiver asclaimed in claim 14, wherein the amplitude correction circuit comprisesa differential stage following the first low pass filter converting theamplitude error into a differential pair of first and second amplitudeerror signals and supplying the same to the first and a secondmultiplier, respectively, and the first and second multiplier areincluded in the in-phase and phase quadrature paths.
 18. A receiver asclaimed in claim 15, wherein the amplitude correction circuit comprisesa differential stage following the first low pass filter converting theamplitude error into a differential pair of first and second amplitudeerror signals and supplying the same to the first and a secondmultiplier, respectively, and the first and second multipliers areincluded in the in-phase and phase quadrature paths.
 19. A receiver asclaimed in claim 16, wherein the phase correction device comprises athird multiplier having a signal input coupled to one of the in-phaseand quadrature paths and a signal output coupled to a first adderdevice, and the first adder device is included in the other of thein-phase and quadrature paths for supplying thereto a part of the signaloccurring at the one path to the other path varying with the phaseerror.
 20. A receiver as claimed in claim 17, wherein the phasecorrection device comprises a third multiplier having a signal inputcoupled to one of the in-phase and quadrature paths and a signal outputcoupled to a first adder device, and the first adder device is includedin the other of the in-phase and quadrature paths for supplying theretoa part of the signal occurring at the one path to the other path varyingwith the phase error.
 21. A receiver as claimed in claim 18, wherein thephase correction device comprises a third multiplier having a signalinput coupled to one of the in-phase and quadrature paths and a signaloutput coupled to a first adder device, and the first adder device isincluded in the other of the in-phase and quadrature paths for supplyingthereto a part of the signal occurring at the one path to the other pathvarying with the phase error.
 22. A receiver as claimed in claim 4,wherein the quadrature phase detectors comprise in-phase and phasequadrature phase detectors, signal inputs thereof being supplied within-phase and phase quadrature IF signals of the pair of quadrature IFsignals, carrier inputs thereof being respectively supplied with phasequadrature and in-phase IF oscillator signals of the pair of quadratureIF oscillator signals and in-phase and phase quadrature outputs thereofbeing coupled to inputs of a subtracting stage, an output of thesubtracting stage being coupled through a loop filter to a control inputof the quadrature IF oscillator.
 23. A receiver as claimed in claim 5,wherein the quadrature phase detectors comprise in-phase and phasequadrature phase detectors, signal inputs thereof being supplied within-phase and phase quadrature IF signals of the pair of quadrature IFsignals, carrier inputs thereof being respectively supplied with phasequadrature and in-phase IF oscillator signals of the pair of quadratureIF oscillator signals and in-phase and phase quadrature outputs thereofbeing coupled to inputs of a subtracting stage, an output of thesubtracting stage being coupled through a loop filter to a control inputof the quadrature IF oscillator.
 24. A receiver as claimed in claim 7,wherein the quadrature phase detectors comprise in-phase and phasequadrature phase detectors, signal inputs thereof being supplied within-phase and phase quadrature IF signals of the pair of quadrature IFsignals, carrier inputs thereof being respectively supplied with phasequadrature and in-phase IF oscillator signals of the pair of quadratureIF oscillator signals and in-phase and phase quadrature outputs thereofbeing coupled to inputs of a subtracting stage, an output of thesubtracting stage being coupled through a loop filter to a control inputof the quadrature IF oscillator.
 25. A receiver as claimed in claim 9,wherein the quadrature phase detectors comprise in-phase and phasequadrature phase detectors, signal inputs thereof being supplied within-phase and phase quadrature IF signals of the pair of quadrature IFsignals, carrier inputs thereof being respectively supplied with phasequadrature and in-phase IF oscillator signals of the pair of quadratureIF oscillator signals and in-phase and phase quadrature outputs thereofbeing coupled to inputs of a subtracting stage, an output of thesubtracting stage being coupled through a loop filter to a control inputof the quadrature IF oscillator.
 26. A receiver as claimed in claim 25,wherein the output of the subtracting stage is coupled to a baseband FMmodulations signal processor.
 27. A receiver as claimed in claim 26,further including a quadrature amplitude demodulator comprising in-phaseand phase quadrature synchronous amplitude detectors, signal inputsthereof being supplied with the in-phase and phase quadrature IFsignals, carrier inputs thereof being respectively supplied with thein-phase and phase quadrature IF oscillator signals and in-phase andphase quadrature outputs thereof being coupled to inputs of an addingstage, an output of the adding stage being coupled through a loop filterto a baseband AM modulation signal processor.